Kanne & Associates

ASIC / FPGA / PLD Design Services

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Kanne & Associates has been designing with PLD's since 1982 and FPGA's since 1985.  We began with Monolithic Memories Inc's (MMI) 16R8  and Xilinx's XC2018  respectively.   In the  years which  followed,  we worked with MMI who was a second source for Xilinx.  

In 1986, We were responsible for one of the only two designs which went into Production for MMI's 64R32 MegaPAL in the United States. (The other was a Tank Design by General Dynamics in Michigan.)

We became a Design Center for EXEL Microelectronics's ERASIC which was the world's first multi-level PLD created as a superset of the popular 22V10 utilizing a folded NOR design.  We operated Design centers in both Central Ohio and Southern California until 1992 when the California location was closed.  A sort wile later Exel Microelectronics ceased to exist.

We have been working heavily with Altera since 1991, first utilizing the Max+II software and currently the Quartus II Design Software. Historically, most of our designs have been created in a Hierarchical Schematic Fashion and not a HDL like VHDL or Verilog.  This might seem unusual at first glance given that we are proficient in VHDL (and AHDL).  However when you stop and realize that as a Design Contractor brought in to work with resources who must later support the designs we create things take on clarity.  Additionally, early design reviews are eased by providing a "birds eye" high level view and later "drilling down" as things take shape.  We have received VHDL training from several sources including Altera.

In recent years following the introduction of the NIOS and Pico/MicroBlaze soft cores we have developed some very complex designs including a Million Gate Ethernet based Device.

Kanne & Associates has experience with the conversion process of FPGA IP and designs into full Volume ASIC Production.  Currently, for this type of need we highly recommend - TekMOS.